參數(shù)資料
型號： CYNSE70064A-83BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Search Engine
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA272
封裝： 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272
文件頁數(shù)： 16/127頁
文件大?。?/td> 3275K
代理商： CYNSE70064A-83BGC
CYNSE70064A
Document #: 38-02041 Rev. *E
Page 16 of 127
7.6
Table 7-5
shows the Read burst address register (RBURREG) fields which must be programmed before a burst Read.
Table 7-5. Read Burst Register Description
Field
Range
Initial Value
ADR
[14:0]
0
Address
. This is the starting address of the data or mask array during a burst
Read operation. It automatically increments by one for each successive
Read of the data or mask array. Once the operation is complete, the contents
of this field must be reinitialized for the next operation.
[18:15]
Reserved
.
BLEN
[27:19]
0
Length of Burst Access
. The device provides the capability to read from
4–511 locations in a single burst. The BLEN decrements automatically. Once
the operation is complete, the contents of this field must be reinitialized for
the next operation.
[67:28]
Reserved
.
Read Burst Address Register
7.7
Table 7-6
describes the Write burst address register (WBURREG) fields which must be programmed before a burst Write.
Table 7-6. Write Burst Register Description
Field
Range
Initial Value
ADR
[14:0]
0
Address
. This is the starting address of the data or mask array during a burst Write
operation. It automatically increments by one for each successive Write of the data or
mask array. Once the operation is complete, the contents of this field must be reini-
tialized for the next operation.
[18:15]
Reserved
.
BLEN
[27:19]
0
Length of Burst Access
. The device provides the capability to Write from 4–511
locations in a single burst. The BLEN decrements automatically. Once the operation is
complete, the contents of this field must be reinitialized for the next operation.
[67:28]
Reserved
.
Write Burst Address Register Description
7.8
Bit [0] of each 68-bit data entry is specially designated for use in the operation of the Learn command. For 68-bit-configured
quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). Every Write and/or Learn command loads
the address of the first 68-bit location that contains a 0 in the entry’s bit[0]. This is stored in the NFA register (see
Table 7-7
). If
all the bits[0] in a device are set to 1, the CYNSE70064A asserts FULO[1:0] to 1.
For 136-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[68]
in a 136-bit word to either 0 or 1 to indicate full or empty status. Both bit[0] and bit[68] must be set to either 0 or 1, (that is, the 10
or 01 settings are invalid).
Table 7-7. NFA Register
Address
60
Reserved
NFA Register
Description
Description
67–15
14–0
Index
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