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參數(shù)資料
| 型號： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 105/127頁 |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 105 of 127
12.5
The following explains the SRAM Read operation accomplished through a table of up to 31 devices, using the following param-
eters: TLSZ = 10. The diagram of such a table is shown in
Figure 12-5
. The following assumes that SRAM access is being
accomplished through CYNSE70064A device number 0, that device number 0 is the selected device.
Figure 12-6
and
Figure 12-7
show the timing diagrams for device number 0 and device number 30, respectively.
Cycle 1A
: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[21:20] on CMD[8:7].
Cycle 1B
: The host ASIC continues to apply the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address.
Cycle 2
: The host ASIC floats DQ[67:0] to a three-state condition.
Cycle 3
: The host ASIC keeps DQ[67:0] in a three-state condition.
Cycle 4
: The selected device starts to drive DQ[67:0].
Cycles 5 to 6
: The selected device continues to drive DQ[67:0].
Cycle 7
: The selected device continues to drive DQ[67:0] and drives an SRAM Read cycle.
Cycle 8
: The selected device drives ACL from Z to LOW.
Cycle 9
: The selected device drives ACK to HIGH.
Cycle 10
: The selected device drives ACK from HIGH to LOW.
At the end of cycle 10, the selected device floats ACL in a three-state condition.
SRAM Read with a Table of up to 31 Devices
cycle
1
CLK2X
CMDV
CMD[1:0]
DQ
Read
Address
OE_L
WE_L
CE_L
SADR
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
TLSZ = 01, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 12-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices
PHS_L
CMD[8:2]
A
B
z
0
1
z
z
1
1
SSV
z
SSF
ALE_L
1
z
z
1
z
z
ACK
z
1
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