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參數(shù)資料
| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 112/127頁(yè) |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 112 of 127
12.8
The following explains the SRAM Write operation done through a table(s) of up to 31 devices with the following parameters
(TLSZ = 10). The diagram of such table(s) is shown in
Figure 12-12
. The following assumes that SRAM access is done through
CYNSE70064A device number 0—device 0 is the selected device.
Figure 12-13
and
Figure 12-14
show the timing diagram for
device number 0 and device number 30, respectively.
Cycle 1A
: The host ASIC applies the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle.
Note
. CMD[2] must be set to 0 for SRAM
Write, as burst Writes into the SRAM are not supported.
Cycle 1B
: The host ASIC continues to apply the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address.
Note
. CMD[2] must be set to 0 for SRAM Write, as burst Writes
into the SRAM are not supported.
Cycle 2
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
Cycle 3
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM
bus with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
SRAM Write with Table(s) of up to 31 Devices
cycle
1
CLK2X
CE_L
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
PHS_L
SADR[21:0]
SSF
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1
SSV
1
0
0
CMDV
CMD[1:0]
CMD[8:2]
01
Write
A B
Address
DQ
z
WE_L
OE_L
0
ALE_L
z
z
ACK
x
x
1
0
1
1
z
1
1
z
1
Figure 12-11. SRAM Write Timing for Device Number 7 in Block of Eight Devices
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