參數(shù)資料
型號： CYNSE70064A-83BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡
英文描述： Search Engine
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA272
封裝： 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272
文件頁數(shù)： 77/127頁
文件大小： 3275K
代理商： CYNSE70064A-83BGC
CYNSE70064A
Document #: 38-02041 Rev. *E
Page 77 of 127
each entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as
part of the SRAM address on the SADR[21:0] lines (See “SRAM Addressing” on page 100.).
Note
. The matching address is
always going to be a location 0 in a four-entry page for 272-bit Search (two LSBs of the matching index will be 00).
The Search command is a pipelined operation and executes Search at one fourth the rate of the frequency of CLK2X for 272-bit
searches in x272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search command
(measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in
Table 10-29
.
Table 10-29. The Latency of Search from C and D cycles to SRAM Access Cycle
Number of Devices
Max Table Size
1 (TLSZ = 00)
8K × 272 bits
1–8 (TLSZ = 01)
64K × 272 bits
1–31 (TLSZ = 10)
248K × 272 bits
The latency of Search from command to SRAM access cycle is 5 for only a single device in the table and TLSZ = 01. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in
Table 10-30
.
Table 10-30. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
10.14
The hardware diagram of the Search subsystem of 31 devices is shown in
Figure 10-57
. Each of the four blocks in the diagram
represents a block of eight CYNSE70064A devices, except the last which has seven devices. The diagram for a block of eight
devices is shown in
Figure 10-58
. The following are the parameters programmed into the 31 devices.
First thirty devices (devices 0–29): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 0, and LDEV = 0.
Thirty-first device (device 30): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 1, and LDEV = 1.
Note
. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in
Table 10-31
. For the purpose of
illustrating the timings, it is further assumed that there is only one device with the matching entry in each block.
Figure 10-59
272-bit Search on Tables Configured as ×272 Using up to 31 CYNSE70064A Devices
Latency in CLK Cycles
4
5
6
Number of CLK Cycles
0
1
2
3
4
5
6
7
Figure 10-56. ×272 Table with Eight Devices
CFG = 10101010
271
0
Location
address
0
4
8
12
262140
(272-bit configuration)
K
GMR
271
0
(First matching entry)
L
A
B
0
1
C
D
2
3
Must be same in each of the eight
devices
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