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參數(shù)資料
| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 46/127頁(yè) |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 46 of 127
The logical 68-bit Search operation is shown in
Figure 10-26
. The entire table (31 devices of 68-bit entries) is compared to a
68-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The
effective GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and
selected by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the
command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the
Comparand Register Index in command’s cycle B. In the ×68 configuration, the even comparand register can be subsequently
used by the Learn command only in the first non-full device. The word K (presented on the DQ bus in both cycles A and B of the
command) is compared with each entry in the table starting at location 0. The first matching entry’s location address L is the
winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 100). The
global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 and LDEV = 1 will be
the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in
Table 10-16
.
Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle
Number of Devices
Max Table Size
1 (TLSZ = 00)
32K × 68 bits
1–8 (TLSZ = 01)
256K × 68 bits
1–31 (TLSZ = 10)
996K × 68 bits
For up to 31 devices in the table (TLSZ = 10), Search latency from command to SRAM access cycle is 6. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in
Table 10-17
.
Table 10-17. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Latency in CLK Cycles
4
5
6
Number of CLK Cycles
0
1
2
3
4
5
6
7
CFG = 00000000
(68-bit configuration)
67
0
Location
address
0
1
2
3
1015807
K
GMR
Comparand Register (odd)
K
Comparand Register (even)
K
67
0
67
0
(First matching entry)
L
Must be same in each of the 31
devices
Will be same in each of the 31
devices
Figure 10-26.
×
68 Table with 31 Devices
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