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參數(shù)資料
| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 12/127頁 |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 12 of 127
WE_L
T
SRAM Write Enable
. This is the Write-enable control for external SRAMs. In a database of
multiple CYNSE70064As, WE_L of all cascaded devices must be connected together. This
signal is then driven by only one of the devices.
SRAM Output Enable
. This is the output-enable control for external SRAMs. Only the last
device drives this signal (with the LRAM bit set).
Address Latch Enable
. When this signal is LOW, the addresses are valid on the SRAM
address bus. In a database of multiple CYNSE70064As, the ALE_L of all cascaded devices
must be connected. This signal is then driven by only one of the devices.
OE_L
T
ALE_L
T
Cascade Interface
LHI[6:0]
I
Local Hit In
. These pins depth-cascade the device to form a larger table. One signal of this
bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. All
unused LHI pins are connected to a logic 0. (For more information, see Section 11.0,
“Depth-Cascading” on page 97.)
Local Hit Out
. LHO[1] and LHO[0] are the same logical signal. Either the LHO[1] or the LHO[0]
is connected to one input of the LHI bus of up to four downstream devices in a block of up to
eight. (For more information see Section 11.0, “Depth-Cascading” on page 97.)
Block Hit In
. Inputs from the previous block BHO[2:0] are tied to BHI[2:0] of the current device.
In a four-block system, the last block can contain only seven devices because the identifi-
cation code 11111 is used for broadcast access.
Block Hit Out
. These outputs from the last device in a block are connected to the BHI[2:0]
inputs of the devices in the downstream blocks.
Full In
. Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device to
generate the FULL flag for the depth-cascaded block.
Full Out
. FULO[1] and FULO[0] are the same logical signal. One of these two signals must
be connected to the FULI of up to four downstream devices in a depth-cascaded table. Bit [0]
in the data array indicates whether the entry is full (1) or empty (0).This signal is asserted if
all bits in the data array are ones. (Refer to Section 11.0, “Depth-Cascading” on page 97, for
information on how to generate the FULL flag.)
Full Flag
. When asserted, this signal indicates that the table of multiple depth-cascaded
devices is full.
LHO[1:0]
O
BHI[2:0]
I
BHO[2:0]
O
FULI[6:0]
I
FULO[1:0]
O
FULL
O
Device Identification
ID[4:0]
I
Device Identification
. The binary-encoded device identification for a depth-cascaded
system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast
address that selects all cascaded search engines in the system. On a broadcast Read-only,
the device with the LDEV bit set to 1 responds.
Supplies
V
DD
V
DDQ
n/a
n/a
Chip Core Supply
. 1.8V.
Chip I/O supply
. 2.5V or 3.3V.
Test Access Port
TDI
TCK
TDO
TMS
TRST_L
I
I
Test access port’s test data in.
Test access port’s test clock.
Test access port’s test data out.
Test access port’s Test Mode Select.
Test access port’s Reset.
T
I
I
Table 5-1. CYNSE70064A Signal Description
(continued)
Type
[1]
Symbol
Description
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CYNSE70128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Network Processing |
| CYNSE70128-83BGC | 制造商:Cypress Semiconductor 功能描述:NETWORK SEARCH ENGINE 388BGA - Trays |
| CYNSE70128-83BGI | 制造商:Cypress Semiconductor 功能描述:NETWORK SEARCH ENGINE 388BGA - Trays |
| CYNSE70129HV-200BGC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70131-250BBC | 制造商:Cypress Semiconductor 功能描述: |
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