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| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 91/127頁(yè) |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 91 of 127
The following is the sequence of operation for a single 272-bit Search command (also refer to Subsection 10.2, “Commands and
Command Parameters” on page 18).
Cycle A
: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for bits [271:136] of the data being searched. DQ[67:0] must be
driven with the 68-bit data ([271:204])to be compared to all locations 0 in the four 68-bits-word page. The CMD[2] signal must
be driven to logic 1.
Note
. CMD[2] = 1 signals that the Search is a ×272-bit Search. CMD[8:7] is ignored in this cycle.
Cycle B
: The host ASIC continues to drive the CMDV HIGH and applies Search command (10) on CMD[1:0]. The DQ[67:0]
is driven with the 68-bit data ([203:136]) to be compared to all locations 1 in the four 68-bits-word page.
Cycle C
: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for the bits [135:0] of the data being searched. CMD[8:7] signals
must be driven with the bits that will be driven by this device on SADR[21:20] if it has a hit. DQ[67:0] must be driven with the
68-bit data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
Cycle D
: The host ASIC continues to drive the CMDV HIGH and continues to apply Search command code (10) on CMD[1:0].
CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and
the hit flag (see page 14 for a description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to
all locations 3 in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x272 tables.
Note
. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR Index in cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles A and B. The GMR
Index in cycle C selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles C and D.
cycle
1
CLK2X
CE_L
OE_L
WE_L
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-69. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table)
PHS_L
SADR[21:0]
SSF
SSV
ALE_L
Search1
(Hit on some
device above.)
Search2
(Hit on some
device above.)
z
0
0
0
0
|(LHI[6:0)]
I(BHI[2:0])
0
Search3
(Hit on some
device above.)
0
BHO[2:0]
0
z
0
1
CMDV
CMD[1:0]
CMD[8:2]
01
01
Search1
Search2
A B A B A B A B
CMD[2]
A B C D A B C D
D1
DQ
D2
A B C D
D3
A B A B
01
Search3
LHO[1:0]
0
z
z
0
0
0
z
0
z
1
1
z
z
z
z
0
0
0
z
z
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