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參數(shù)資料
| 型號： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 14/127頁 |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 14 of 127
7.2
The device contains 16 68-bit global mask registers (eight pairs) dynamically selected in every Search operation to select the
Search subfield. The addressing of these registers is explained in
Figure 7-2
. The three-bit GMR Index supplied on the command
(CMD) bus can apply eight pairs of global masks during the Search and Write operations, as shown below.
Note
. In 68-bit Search
and Write operations, the host ASIC must program both the even and odd mask registers with the same values.
68
Mask Registers
Each mask bit in the GMRs is used during Search and Write operations. In Search operations, setting the mask bit to 1 enables
compares; setting the mask bit to 0 disables compares (forced match) at the corresponding bit position. In Write operations to
the data or mask array, setting the mask bit to 1 enables Writes; setting the mask bit to 0 disables Writes at the corresponding
bit position.
7.3
The device contains eight search successful registers (SSRs) to hold the index of the location where a successful Search
occurred. The format of each register is described in
Table 7-2
. The Search command specifies which SSR stores the index of
a specific Search command in cycle B of the Search instruction. Subsequently, the host ASIC can use this register to access that
data array, mask array, or external SRAM using the index as part of the indirect access address (see
Table 10-4
and
Table 10-7
).
The device with a valid bit set performs a Read or Write operation. All other devices suppress the operation.
Table 7-2. Search Successful Register Description
Field
Range
Initial Value
INDEX
[14:0]
X
Index
. This is the address of the 68-bit entry where a successful Search occurs.
The device updates this field only when the Search is successful. If a hit occurs
in a 136-bit entry-size quadrant, the LSB is 0. If a hit occurs in a 272-bit entry-size
quadrant, the two LSBs are 00. This index updates if the device is either a local
or global winner in a Search operation.
–
[30:15]
0
Reserved
.
VALID
[31]
0
Valid
. During Search operation in a depth-cascaded configuration, the device
that is a global winner in a match sets this bit to 1. This bit updates only when
the device is a global winner in a Search operation.
–
[67:32]
0
Reserved
.
Search Successful Registers (SSR[0:7])
7.4
Table 7-3
describes the command register fields.
Table 7-3. Command Register Description
Field
Range
Initial Value
SRST
[0]
0
Command Register
Description
Description
Software Reset
. If 1, this bit resets the device with the same effect as a hardware reset.
Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically resets
to a 0 after the reset has completed.
Device Enable
. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and ALE_L), SSF,
and SSV signals in three-state condition and forces the cascade interface output signals
LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose of this bit is
to make sure that there are no bus contentions when the devices power up in the system.
DEVE
[1]
0
0
1
2
3
4
5
6
7
0
2
4
6
8
1
3
5
7
9
11
13
15
10
12
14
Index
135
68
Search and Write Command Global Mask Selection
Figure 7-2. Addressing the Global Masks Register Array
0
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