參數(shù)資料
型號： CYNSE70064A-83BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Search Engine
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA272
封裝： 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272
文件頁數(shù)： 20/127頁
文件大?。?/td> 3275K
代理商： CYNSE70064A-83BGC
CYNSE70064A
Document #: 38-02041 Rev. *E
Page 20 of 127
Cycle 3
: The host ASIC keeps DQ[67:0] in three-state condition.
Cycle 4
: The selected device starts to drive the DQ[67:0] bus, and drives the ACK signal from Z to LOW.
Cycle 5
: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
signal HIGH.
Cycle 6
: The selected device floats the DQ[67:0] to three-state condition and drives the ACK signal LOW.
At the termination of cycle 6, the selected device releases the ACK line to three-state condition. The Read instruction is complete,
and a new operation can begin. Note that the latency of the SRAM Read will be different than the one described above (see
Subsection 12.2, “SRAM PIO Access” on page 101).
Table 10-4
lists and describes the format of the Read address for a data
array, mask array, or SRAM.
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM
Table 10-5
describes the Read address format for the internal registers.
Figure 10-2
illustrates the timing diagram for the burst
Read of the data or mask array.
Table 10-5. Read Address Format for Internal Registers
DQ[67:26]
DQ[25:21]
DQ[20:19]
Reserved
ID
11: Register
The Read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the
starting address (ADR) and the length of the transfer (BLEN) before initiating the burst Read command.
Note:
6.
“ | ” stands for logical OR operation. “{}” stands for concatenation operator.
DQ[67:30]
Reserved
DQ[29]
0: Direct
1: Indirect
DQ[28:26]
SSRI (applicable
if DQ[29] is
indirect)
DQ[25:21] DQ[20:19]
ID
DQ[18:15]
Reserved If DQ[29] is 0, this field carries the address of the data
array location. If DQ[29] is 1, the SSRI specified on
DQ[28:26] is used to generate the address of the data
array location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
[6]
Reserved If DQ[29] is 0, this field carries the address of the mask
array location. If DQ[29] is 1, the SSRI specified on
DQ[28:26] is used to generate the address of the mask
array location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
[6]
Reserved If DQ[29] is 0, this field carries the address of the SRAM
location. If DQ[29] is 1, the SSRI specified on DQ[28:26]
is used to generate the address of the SRAM location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}
[6]
DQ[14:0]
00: Data
Array
Reserved
0: Direct
1: Indirect
SSRI (applicable
if DQ[29] is
indirect)
ID
01: Mask
Array
Reserved
0: Direct
1: Indirect
SSRI (applicable
if DQ[29] is
indirect)
ID
10:
External
SRAM
DQ[18:6]
Reserved
DQ[5:0]
Register Address
CMDV
CMD[1:0]
ACK
EOT
DQ
FF
FF
Data1
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
cycle
11
cycle
12
Data0
Data2
FF
Data3
FF
PHS_L
CMD[8:2]
Address
A B
Read
CLK2X
Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
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