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| 型號(hào)： | ARM610 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 97/173頁(yè) |
| 文件大小： | 897K |
| 代理商： | ARM610 |
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Instruction and Data Cache (IDC)
ARM610 Data Sheet
6-3
6.4.2 Uncacheable reads
C = 0
The cache is not searched for the relevant data; instead an external memory access
is initiated. No linefetch operation is performed, and the cache is not updated.
6.4.3 Updateable writes
U = 1
An external memory access is initiated, and the cache is searched; if the cache holds
a copy of the data from the address being written to, then the cache data is
simultaneously updated.
6.4.4 Non-updateable writes
U = 0
An external memory access is initiated, but the cache is not searched and the contents
of the cache are not affected.
6.5
IDC Validity
The IDC operates with virtual addresses, so care must be taken to ensure that its
contents remain consistent with the virtual to physical mappings performed by the
Memory Management Unit. If the Memory Mappings are changed, the IDC validity
must be ensured.
6.5.1 Software IDC flush
The entire IDC may be marked as invalid by writing to the ARM610 IDC Flush Register
(Register 7). The cache will be flushed immediately the register is written, but note that
the following two instruction fetches may come from the cache before the register is
written.
6.5.2 Doubly mapped space
Since the cache works with virtual addresses, it is assumed that every virtual address
maps to a different physical address. If the same physical location is accessed by more
than one virtual address, the cache cannot maintain consistency, since each virtual
address will have a separate entry in the cache, and only one entry will be updated on
a processor write operation. To avoid any cache inconsistencies, both doubly-mapped
virtual addresses should be marked as uncacheable.
6.6
Read-Lock-Write
The IDC treats the Read-Locked-Write instruction as a special case. The read phase
always forces a read of external memory, regardless of whether the data is contained
in the cache. The write phase is treated as a normal write operation (and if marked as
updateable, and the data is already in the cache, the cache will be updated). Externally
the two phases are flagged as indivisible by asserting the
LOCK
signal.
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