參數(shù)資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 38/173頁
文件大?。?/td> 897K
代理商： ARM610
Instruction Set - Data processing
ARM610 Data Sheet
4-10
O
Figure 4-3: Data processing instructions
The instruction produces a result by performing a specified arithmetic or logical
operation on one or two operands. The first operand is always a register (Rn).
The second operand may be a shifted register (Rm) or a rotated 8-bit immediate value
(Imm) according to the value of the I bit in the instruction. The condition codes in the
CPSR may be preserved or updated as a result of this instruction, according to the
value of the S bit in the instruction.
Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used
only to perform tests and to set the condition codes on the result and always have the
S bit set. The instructions and their effects are listed in
processing instructions
on page 4-10
.
·
Table 4-3: ARM Data
4.4.1 CPSR flags
The data processing operations may be classified as
logical
or
arithmetic.
Logical operations
The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the
logical action on all corresponding bits of the operand or operands to produce the
result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be
unaffected, the C flag will be set to the carry out from the barrel shifter (or preserved
when the shift operation is LSL #0), the Z flag will be set if and only if the result is all
zeros, and the N flag will be set to the logical value of bit 31 of the result
.
Assembler
Mnemonic
OpCode
Action
AND
0000
operand1 AND operand2
EOR
0001
operand1 EOR operand2
SUB
0010
operand1 - operand2
RSB
0011
operand2 - operand1
ADD
0100
operand1 + operand2
ADC
0101
operand1 + operand2 + carry
SBC
0110
operand1 - operand2 + carry - 1
RSC
0111
operand2 - operand1 + carry - 1
TST
1000
as AND, but result is not written
TEQ
1001
as EOR, but result is not written
CMP
1010
as SUB, but result is not written
CMN
1011
as ADD, but result is not written
ORR
1100
operand1 OR operand2
Table 4-3: ARM Data processing instructions
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