參數(shù)資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 108/173頁
文件大小： 897K
代理商： ARM610
Memory Management Unit
ARM610 Data Sheet
9-4
access permission data, resides in a translation table located in physical memory. The
MMU provides the logic needed to traverse this translation table, obtain the translated
address, and check the access permission.
There are three routes by which the address translation (and hence the permission
check) takes place. The route taken depends on whether the address in question has
been marked as a section-mapped access or a page-mapped access; and there are
two sizes of page-mapped access (large pages and small pages). However, the
translation process always starts out in the same way, as described below, with a Level
One fetch. A section-mapped access only requires a Level One fetch, but a page-
mapped access also requires a Level Two fetch.
9.4
Translation Process
9.4.1 Translation Table Base
The translation process is initiated when the on-chip TLB does not contain an entry for
the requested virtual address. The Translation Table Base (TTB) Register points to the
base of a table in physical memory which contains Section and/or Page descriptors.
The 14 low-order bits of the TTB Register are set to zero as illustrated in
Translation table base register
; the table must reside on a 16Kb boundary.
·
Figure 9-2:
Figure 9-2: Translation table base register
9.4.2 Level One Fetch
Bits 31:14 of the Translation Table Base register are concatenated with bits 31:20 of
the virtual address to produce a 30-bit address as illustrated in
the translation table first level descriptors
. This address selects a four-byte translation
table entry which is a First Level Descriptor for either a Section or a Page (bit 1 of the
descriptor returned specifies whether it is for a Section or Page).
·
Figure 9-3: Accessing
0
13
14
31
Translation Table Base
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