參數(shù)資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 116/173頁
文件大?。?/td> 897K
代理商： ARM610
Memory Management Unit
ARM610 Data Sheet
9-12
9.12 MMU Faults and CPU Aborts
The MMU generates four types of faults:
Alignment
Translation
Domain
Permission
In addition, an external abort may be raised on external data access.
The access control mechanisms of the MMU detect the conditions that produce these
faults. If a fault is detected as the result of a memory access, the MMU will abort the
access and signal the fault condition to the CPU. The MMU is also capable of retaining
status and address information about the abort. The CPU recognises two types of
abort: data aborts and prefetch aborts, and these are treated differently by the MMU.
If the MMU detects an access violation, it will do so before the external memory access
takes place, and it will therefore inhibit the access. External aborts will not necessarily
inhibit the external access, as described in the section on external aborts.
9.13 Fault Address and Fault Status Registers (FAR and FSR)
Aborts resulting from data accesses (data aborts) are acted upon by the CPU
immediately, and the MMU places an encoded 4-bit value FS[3:0], along with the 4-bit
encoded Domain number, in the Fault Status Register (FSR). In addition, the virtual
processor address which caused the data abort is latched into the Fault Address
Register (FAR). If an access violation simultaneously generates more than one source
of abort, they are encoded in the priority given in
·
Table 9-4: Priority encoding of fault
status
CPU instructions on the other hand are prefetched, so a prefetch abort simply flags
the instruction as it enters the instruction pipeline. Only when (and if) the instruction is
executed does it cause an abort; an abort is not acted upon if the instruction is not
used (ie. it is branched around). Because instruction prefetch aborts may or may not
be acted upon, the MMU status information is not preserved for the resulting CPU
abort; for a prefetch abort, the MMU does not update the FSR or FAR.
The sections that follow describe the various access permissions and controls
supported by the MMU and detail how these are interpreted to generate faults.
Source
FS[3210]
Domain[3:0]
FAR
Highest
Write Buffer
00x0
x
Note 3
Bus Error (linefetch)
Section
0100
valid
Note 4
Page
0110
valid
valid
Bus Error (other)
Section
1000
valid
valid
Table 9-4: Priority encoding of fault status
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