參數(shù)資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 55/173頁
文件大?。?/td> 897K
代理商： ARM610
Instruction Set - LDR, STR
ARM610 Data Sheet
4-27
O
A word store (STR) should generate a word aligned address. The word presented to
the data bus is not affected if the address is not word aligned. That is, bit 31 of the
register being stored always appears on data bus output 31.
4.7.4 Use of R15
Write-back must not be specified if R15 is specified as the base register (Rn). When
using R15 as the base register you must remember it contains an address 8 bytes on
from the address of the current instruction.
R15 must not be specified as the register offset (Rm).
When R15 is the source register (Rd) of a register store (STR) instruction, the stored
value will be address of the instruction plus 12.
4.7.5 Restriction on the use of base register
When configured for late
aborts, the following example code is difficult to unwind as
the base register, Rn, gets updated before the
abort handler starts. Sometimes it may
be impossible to calculate the initial value.
After an abort, the following example code is difficult to unwind as the base register,
Rn, gets updated before the
abort handler starts. Sometimes it may be impossible to
calculate the initial value.
Example:
LDR
R0,[R1],R1
Therefore a post-indexed LDR or STR where Rm is the same register as Rn should
not be used.
4.7.6 Data aborts
A transfer to or from a legal address may cause problems for a memory management
system. For instance, in a system which uses virtual memory the required data may
be absent from main memory. The memory manager can signal a problem by taking
the processor
ABORT
input HIGH whereupon the Data Abort trap will be taken. It is
up to the system software to resolve the cause of the problem, then the instruction can
be restarted and the original program continued.
4.7.7 Instruction cycle times
Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental
cycles, where S,N and I are as defined in
·
6.2 Cycle Typeson page 6-2.
STR instructions take 2N incremental cycles to execute.
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