參數(shù)資料
型號(hào)： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 25/173頁
文件大小： 897K
代理商： ARM610
Programmer’s Model
ARM610 Data Sheet
3-9
When ARM610 takes the undefined instruction trap it performs the following:
1
Saves the address of the Undefined or coprocessor instruction plus 4 in
R14_und; saves CPSR in SPSR_und
2
Forces M[4:0]=11011 (Undefined mode) and sets the I bit in the CPSR
3
Forces the PC to fetch the next instruction from address 0x04
To return from this trap after emulating the failed instruction, use MOVS PC,R14_und.
This will restore the CPSR and return to the instruction following the undefined
instruction.
3.5.6 Vector summary
These are byte addresses, and will normally contain a branch instruction pointing to
the relevant routine.
The FIQ routine might reside at 0x1C onwards, and thereby avoid the need for (and
execution time of) a branch instruction.
The reserved entry is for an Address Exception vector which is only operative when
the processor is configured for a 26-bit program space. See
Compatibility
.
·
Chapter A, Backward
Address
Exception
Mode on entry
0x00000000
Reset
Supervisor
0x00000004
Undefined instruction
Undefined
0x00000008
Software interrupt
Supervisor
0x0000000C
Abort (prefetch)
Abort
0x00000010
Abort (data)
Abort
0x00000014
-- reserved --
--
0x00000018
IRQ
IRQ
0x0000001C
FIQ
FIQ
Table 3-2: Vector summary
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