參數(shù)資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 130/173頁
文件大?。?/td> 897K
代理商： ARM610
Bus interface
ARM610 Data Sheet
10-6
Figure 10-5: Linefetch
10.8.4 Translation Fetches
These accesses are required to obtain the translation data for an access. There are
two types:
Level 1
A Level 1 access is required for a section-mapped memory location.
Level 2
A Level 2 access is required for a page mapped memory location. A
Level 2 access is always preceded by a Level 1 access.
Translation fetches are often immediately followed by a data access. In fact the
translation fetch held up the data access because the translation was not contained in
the Translation Lookaside Buffer (TLB). Translation fetches are always read word
accesses. So if a byte or write (or both) access is not possible because the address is
not contained in the TLB, the access would be preceded by the translation fetch(es),
which will always be word read accesses.
Figure 10-6: Translation table-walking sequence (write) for page
MCLK
A[31:0]
nMREQ
READ
D[31:0]
a
a+4
a+8
a+12
Level 2 Address
MCLK
A[31:0]
nMREQ
nRW
WRITE
D[31:0]
READ
D[31:0]
Level 1 Address
Physical Address
Page Table Entry
Page Table Descriptor
Write Data
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