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參數(shù)資料
| 型號： | ARM610 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁數(shù)： | 8/173頁 |
| 文件大?。?/td> | 897K |
| 代理商： | ARM610 |
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Introduction
ARM610 Data Sheet
1-2
1.1
Introduction
ARM610, is a general purpose 32-bit microprocessor with 4kByte cache, write buffer
and Memory Management Unit (MMU) combined in a single chip. The CPU within
ARM610 is the ARM6. The ARM610 is software compatible with the ARM processor
family and can be used with ARM support chips, eg. I/O, memory and video.
The ARM610 architecture is based on 'Reduced Instruction Set Computer' (RISC)
principles, and the instruction set and related decode mechanism are greatly simplified
compared with microprogrammed 'Complex Instruction Set Computers' (CISC).
The on-chip mixed data and instruction cache together with the write buffer
substantially raise the average execution speed and reduce the average amount of
memory bandwidth required by the processor. This allows the external memory to
support additional processors or Direct Memory Access (DMA) channels with minimal
performance loss.
The MMU supports a conventional two-level page-table structure and a number of
extensions which make it ideal for embedded control, UNIX and Object Oriented
systems.
The instruction set comprises ten basic instruction types:
Two of these make use of the on-chip arithmetic logic unit, barrel shifter and
multiplier to perform high-speed operations on the data in a bank of 31
registers, each 32 bits wide.
Three classes of instruction control data transfer between memory and the
registers, one optimised for flexibility of addressing, another for rapid context
switching and the third for swapping data.
Two instructions control the flow and privilege level of execution.
Three types are dedicated to the control of external coprocessors which allow
the functionality of the instruction set to be extended off-chip in an open and
uniform way.
The ARM instruction set is a good target for compilers of many different high-level
languages. Where required for critical code segments, assembly code programming is
also straightforward, unlike some RISC processors which depend on sophisticated
compiler technology to manage complicated instruction interdependencies.
The memory interface has been designed to allow the performance potential to be
realised without incurring high costs in the memory system. Speed-critical control
signals are pipelined to allow system control functions to be implemented in standard
low-power logic, and these control signals permit the exploitation of paged mode
access offered by industry standard DRAMs.
ARM610 is a fully static part and has been designed to minimise its power
requirements. This makes it ideal for portable applications where both these features
are essential.
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