參數(shù)資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 90/173頁
文件大?。?/td> 897K
代理商： ARM610
Configuration
ARM610 Data Sheet
5-2
5.1
Configuration
The operation and configuration of ARM610 is controlled both directly via coprocessor
instructions and indirectly via the Memory Management Page tables. The coprocessor
instructions manipulate a number of on-chip registers which control the configuration
of the Cache, write buffer, MMU and a number of other configuration options.
To ensure backwards compatibility of future CPUs, all reserved or unused bits in
registers and coprocessor instructions should be programmed to '0'. Invalid registers
must not be read or written. The following bits should be programmed to '0'.
Register 1 bits[31:9]
Register 2 bits[13:0]
Register 5 bits[31:0]
Register 6 bits[11:0]
Register 7 bits[31:0]
Note:
The grey areas in the register and translation diagrams are reserved and should be
programmed 0 for future compatibility.
5.2
Internal Coprocessor Instructions
The on-chip registers may be read using MRC instructions and written using MCR
instructions. These operations are only allowed in non-user modes and the undefined
instruction trap will be taken if accesses are attempted in user mode.
Figure 5-1: Format of internal coprocessor instructions MRC and MCR
5.3
Registers
ARM610 contains registers which control the cache and MMU operation. These
registers are accessed using CPRT instructions to Coprocessor #15 with the
processor in a privileged mode. Only some of registers 0-7 are valid: an access to an
invalid register will cause neither the access nor an undefined instruction trap, and
therefore should never be carried out; an access to any of the registers 8-15 will cause
the undefined instruction trap to be taken.
1 1 1 0
n
1 1 1 1
1
0
3
4
5
7
8
11
12
15
16
19
20
21
23
24
27
28
31
Cond
CRn
Rd
ARM condition codes
ARM610 Register
ARM Register
-1 MRC register read
0 MCR register write
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