參數(shù)資料
型號: AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 94/99頁
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
PLL CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x46 ]
PLL control register.
Sub Address 0x46
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved
LPGAUTO
LPG3
LPG2
LPG1
LPG0
LPGM1
LPGM2
Default Value
0
PLL Control Register Definition
BIT
Register Name
R/W
Definition
bit 0
bit 1
LPGM2:LPGM
1
Loop Gain Control bit
R/W
FRAME LOCK Mode EC gain
LPGM[1:2] =
00 : x 1 (Default
01 : x 2
10 : x 4
11 : x 8
bit 2
bit 5
LPG0:LPG3
Loop Gain Control bit
R/W
LPG[1:0] Line Lock mode EC gain[1:0]
00 : x 1 (Default
10 : x 4
LPG[3] GM gain
01 : x 1/2
11 : x 2
LPG[2] CP gain
0 : x 1 (Default
1 : x 2
0 : x 1 (Default)
1 : x 2
LPGAUTO
Loop Gain Auto bit
R/W
1 : Auto
In case of Auto mode setting, LPG2 and LPG3
settings are ignored and the CP and GM gains
are switched automatically depending on the
PLL mode.
CP x 1 (Low), GM : x1 (Low)
Frame-Lock mode :
CP : x 2 (High) , GM : x 2 (High)
Reserved bit
R/W
Reserved
bit 6
0 : Manual Default
Line-Lock mode:
bit 7
Reserved
Rev.0
94
2003/01
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