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參數(shù)資料
| 型號(hào)： | AK8850 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | NTSC Digital Video Decoder |
| 中文描述： | NTSC制式數(shù)字視頻解碼器 |
| 文件頁(yè)數(shù)： | 75/99頁(yè) |
| 文件大?。?/td> | 1757K |
| 代理商： | AK8850 |
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ASAHI KASEI
[AK8850]
CLAMP CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x0A ]
This register controls clamp-related matters. Reserved bits must be set to “ 0 “.
Sub Address 0x0A
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
Bit 3
bit 2
bit 1
bit 0
ACLMP
INCLPTMG
FBCLPTMG1
FBCLPTMG0
CLPLVL1
CLPLVL0
Default Value
0
UNMASK
Reserved
Clamp Control Register
BIT
Register Name
R/W
Definition
bit 0
bit 1
CLPLVL0
~
CLPLVL1
CLAMP Level 0
~
CLAMP Level1 bit
R/W
Setting analog video clamp. This setting is valid
for Clamp 1. The level of Clamp 2/3 is constant
at 512 level.
CLPLVL1 CLPLVL0
00: 16 [default]
01: 240
10: 252
11: Analog clamp is off
bit 2
bit 3
FBCLPTMG0
~
FBCLPTMG1
Feed Back Clamp Timing bit
R/W
Setting the clamp timing pulse.
00 : Synctip level clamp with the internal clamp
timing [default]
01 : Synctip level clamp with the external clamp
timing pulse.
10 : Pedestal level clamp with the internal clamp
timing pulse.
11 : Pedestal level clamp with the external clamp
timing pulse.
bit 4
INCLPTMG
Input Clamp Timing bit
Setting the clamp timing pulse.
0 : Internal Clamp timing pulse [default]
1 : External Clamp timing pulse
bit 5
ACLAMP
Analog Clamp On/Off bit
R/W
Setting the clamp on/off.
When a video signal is input through AC
coupling capacitor, this set must be set to “0”.
0 : ON
[default]
1 : OFF (AIN Clamp OFF)
bit 6
Reserved
Reserved bit
R/W
Reserved
bit 7
UNMASK
Clamp Unmask bit
R/W
Clamp mask on/off bit.
Normally this bit set to 0.
0 : Masked [default]
1 : Unmasked
Rev.0
77
2003/01
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