參數(shù)資料
型號(hào): AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁(yè)數(shù): 71/99頁(yè)
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
OUTPUT CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x05 ]
Thie register sets the external output signal attributes like HSYNC, VSYNC, FIELD, DVALID and FRAME etc. Timing of
output signals can be altered by CLKOUT-bit set.
Sub Address 0x05
Default Value : 0x14
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VDVSYNC
FFDELAY
HALFCLK
FRAME
DVALVLK
FIELD
VSYNC
HSYNC
Default Value
0
1
0
1
0
Output Control Register Definition
BIT
Register Name
Definition
bit 0
0 : Low [default]
HSYNC
HSYNC-Logic bit
R/W
1 : High
bit 1
R/W
1 : High
VSYNC
VSYNC-Logic bit
0 : Low[default]
bit 2
R/W
FIELD
FIELD-Logic bit
0 : ODD FIELD : Low
1 : ODD FIELD : High [default]
bit 3
DVAL/VLK
DVALID VLock Switch- bit
R/W
0 : DVALID signal output [default]
1 : VLOCK status output
bit 4
FRAME
FRAME-Logic bit
R/W
0 : Low at CF = 0
1 : High at CF = 0[default]
bit 5
HALFCLK
HALFCLK-bit
R/W
0 : Low at Y-data ouput timing [ Default]
1 : Hight at Y-data output
bit 6
FFDELAY
Field Frame Delay bit
R/W
Field timing signal and Frame timing signal can
be output 0.5H delayed with this bit.
0 : No Delay [default]
bit 7
VDVSYNC
VD/VSYNC Select bit
R/W
0 : Output VSYNC Pulse [default]
1 : Ouput VD pulse.
(Refer to the Figure “Output timing Signal”)
R/W
1 : 0.5H Delay
FIELD and FRAME signals are correct values only when the Standard signal is input. ( in case of Non-Standard signal
input, FIELD and FRAME signals are not necessarily correct ones .For handling of Non-Standard signal input,refer to item
7-4-21 ).
Rev.0
73
2003/01
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