參數(shù)資料
型號(hào)： AK8850
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： NTSC Digital Video Decoder
中文描述： NTSC制式數(shù)字視頻解碼器
文件頁(yè)數(shù)： 67/99頁(yè)
文件大小： 1757K
代理商： AK8850
ASAHI KASEI
[AK8850]
3. Pin Functional Description
Pin
Number
Identification
I/O
Description
2
SCL
I
I2C bus Clock
3
SDA
I/O
I2C bus Data (Open Collector )
4
SELA
I
I2C bus address selector
6
FIELD
O
FIELD Identify
Low EVEN
High ODD
7
HSYNC
O
HSYNC Timing output pin
8
VSYNC
O
VSYNC Timing output pin. (It is possible to output V_Blank Signal (VD) by
setting a register)
11
D7 (MSB)
O
Decoded data output pin (MSB)
12
D6
O
15
D5
O
16
D4
O
19
D3
O
20
D2
O
23
D1
O
Decoded data output pin
24
D0 (LSB)
O
Decoded data output pin (LSB)
31
DVALID/VLOCK
O
Active Video Timing signal (720 Pixel)
It can also output VLOCK status by setting a register.
34
FRAME1/CSYNC
O
35
FRAME0
O
When a standard signal is input, a color frame signal is output.
When a non-standard signal input, this pin outputs a timing signal that is
toggled every 525/625 lines.
FRAME1 pin can output the CYSNC signal by setting a register.
36
HALFCLKOUT
O
When Rec.656 data is output, this signal identifies the signal as Y or C.
(This rate is about 13.5MHz)
39
CLK27MOUT
O
Output Timing of output data (About 27MHz)
40
NSIG
O
When No-signal is input this pin goes High.
41
NSTD
O
When Non-standard signal is input, this pin goes High.
49
CLKINV
I
This pin decides the polarization of CLK27MOUT.
50
/RESET
I
Reset Signal input pin. (Low Active)
After Power up or power down mode, Reset signal should be Low at least
10msec.
52
CLK
I
Input 27MHz Clock.
54
EXTCLP
I/O
External Clamp timing input pin.
58
LLPF
O
Connect Loop Filter for Line Lock clock.
59
LLPFC
O
Connect Capacitors for Line Lock clock.
60
FLPF
O
Connect Loop Filter for Frame Lock clock.
61
FLPFC
O
Connect Capacitors for Frame Lock clock.
62
VREFOUT
O
Internal Voltage Reference output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
63
IVCXO
O
Control voltage output pin for the external VCXO.
Connect via a resistor to AVSS.
64
IRefR1
O
Terminate with 13k resistor (0.1% accuracy) to AVSS.
This Register sets the reference current for the PLL Block.
65
IRefR2
O
Terminate with 4.7k Register (0.1% accuracy) between AVSS.
This Register sets the internal reference current.
66
VCOM
O
Internal common voltage for ADC output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
67
VRN
O
Internal negative voltage for ADC output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
68
VRP
O
Internal positive voltage for ADC output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
69
FBCAP3
O
Terminate using a 0.033uF capacitor between AVSS. (for Clamp Level)
Rev.0
7
2002/01
相關(guān)PDF資料
PDF描述
AKA103 16 SEG ALPHANUMERIC DISPLAY, SUPER BRIGHT ORANGE, 25.4 mm
AKD4112B AKD4112B EVALUATION BOARD
AKD4552 3V 96KHZ 24BIT CODEC
AKD4640 AKD4640 EVALUATION BOARD
AL-12-60 12 A, SILICON, BRIDGE RECTIFIER DIODE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK-8850 功能描述:機(jī)架和機(jī)柜配件 ANCHOR KIT SEISMIC R RoHS:否 制造商:Bivar 產(chǎn)品:Rack Accessories 面板空間: 顏色:Black
AK8851 制造商:AKM 制造商全稱(chēng):AKM 功能描述:NTSC/PAL/SECAM Digital Video Decoder
AK8851VQ 制造商:AKM 制造商全稱(chēng):AKM 功能描述:NTSC/PAL/SECAM Digital Video Decoder
AK8853VN 制造商:AKM 制造商全稱(chēng):AKM 功能描述:NTSC/PAL/SECAM Digital Video Decoder
AK8853XQ 制造商:AKM 制造商全稱(chēng):AKM 功能描述:NTSC/PAL/SECAM Digital Video Decoder
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*