參數(shù)資料
型號: AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 9/99頁
文件大小: 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
5. Output Signal Timing Description
5-1. NTSC Input
Vertical Sync timing, Field signal and Frame signal timing relations are shown below. The logic states of HSYNC/VSYNC/FIELD/FRAME can be altered via register settings. Depending
on the register setting either VSYNC or VD signal is available. FIELD output and FRAME output signals change states on the rising edge of CSYNC just before the 0.5H delay period that
is controlled by the Output Control Register. The 0.5H delay timing is shown on page 18.
Note)
Frame timing signal output is as shown above when standard signals are input to the AK8850. If a Non-standard signal is input to AK8850, the number of Color frame is not guaranteed. When the
input signal changes from non-standard to standard, that the Frame timing signal may not change for 512 lines (max) as the AK8850 synchronizes to the input video signal.
VSYNC
FIELD
EVEN
ODD
EVEN
ODD
52
1
2
3
4
5
6
7
8
9
10
11
FRAME
FIELD
FRAME
VSYNC
(Low)
FIELD
EVEN
ODD
FRAME
26
27
26
27
26
EVEN
ODD
FIELD
FRAME
VSYNC
(High
26
27
26
27
26
HSYNC
CSYNC
HSYNC
52
1
2
3
4
5
6
7
8
9
10
11
CSYNC
HSYNC
VSYNC
CSYNC
HSYNC
VD
Rev.0
17
2002/0
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