參數(shù)資料
型號(hào): AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 39/99頁
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
7-4 DIGITAL SIGNAL PROCESSING FUNCTIONAL SPECIFICATION
7-4-1 Decimation Filter
Composite, YC, and Component input signals are sampled at 27 MHz and then are down- sampled to 13.5 MHz by the
Decimation Filter. The Frequency Response of the Decimation Filter is shown as follows.
-70
-60
-50
-40
-30
-20
-10
0
10
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0 11.0 12.0 13.0
Frequency [MHz]
Ga
in
[
d
B]
7-4-2 SYNC-Separation, SYNC-Detection, Phase-Error Detection
This detects SYNC-signal position of the discrete signal. The detected SYNC signal controls the PLL.
7-4-3 DIGITAL PEDESTAL CLAMP
This sets the digitized data Pedestal position 240 / 252 levels ( 286 mV-type SYNC / 300 mV-type SYNC ). This function
decreases the effect of SYNC level depth variations in the video. The control-time-constant and non-sensing bandwidth
can be set by the [ CONTROL 2 REGISTER ].
For 286 mV-type SYNC and 300 mV-type SYNC details, please refer to [ Table 7-2-1-1 ] in section [ 7-2-1 INPUT SIGNAL
SELECTOR MODE ].
Digital Pedestal Clamp Control Register description :
* [ CONTROL 2 REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CLKMODE1
CLKMODE0
ACC1
ACC0
DPCC1
DPCC0
DPCT1
DPCT0
Default Value
1
0
1
The control-time-constant is set by the [ DPCT1 : DPCT0 ]-bit ,and the non-sensing bandwidth is set by the [ DPCC1 :
DPCC0 ]-bit.
[DPCT1:DPCT0]
Pedestal Clamp
Time Constance
00
OFF
01
Fast
(Default)
About 1.5-Lines
10
Middle
About 3.5-Lines
11
Slow
About 7.5-Lines
Rev.0
44
2003/01
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