參數(shù)資料
型號: AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 92/99頁
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
CLOCK CONTROL-1 REGISTER ( R /W ) [ SUB ADDRESS 0x36 ]
This register controls the Clock transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select
( CONTROL 2 REGISTER ( 0x09 ))
Sub Address 0x36
Default Value : 0x84
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TTC0
SKEWTH4
SKEWTH3
SKEWTH2
SKEWTH1
SKEWTH0
Default Value
0
1
0
TTC1
SKEWTH5
1
0
Clock Control-1 Register Definition
BIT
R/W
bit 0
~
bit 5
SKEWTH0
SKEWTH5
Skew Detection Threshold
R/W
Set the threshold value for VTR Skew detection.
Threshold value = [SKEWTH5:SKEWTH0]
bit 6
bit 7
Clock Transition Time Constant
TTC0
TTC1
Time Constant for clock mode transition.
0 : slowest
3 : fastest
Register Name
Definition
CLOCK CONTROL-2 REGISTER ( R / W ) [ SUB ADDRESS 0x37 ]
This register controls the Clock Transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select Control
2 Register ( 0x09 ).
Sub Address 0x37
Default Value : 0x7C
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LNFRTH7
LNFRTH6
LNFRTH5
LNFRTH4
LNFRTH3
LNFRTH2
LNFRTH1
LNFRTH0
Default Value
1
0
1
Clock Control-2 Register Definition
BIT
Register Name
R/W
bit 0
~
bit 7
LNFRTH0
LNFRTH7
Lint to Frame Threshold Level
Control bit
R/W
The threshold parameter from Line-Lock clock
mode to Frame-Lock clock mode.
Definition
Rev.0
92
2003/01
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