參數(shù)資料
型號: AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 93/99頁
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
CLOCK CONTROL- 3 REGISTER ( R / W ) [ SUB ADDRESS 0x38 ]
This register controls the Clock Transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select
Control 2 Register ( 0x09 ).
Sub Address 0x38
Default Value : 0x3C
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FRLNTH7
FRLNTH6
FRLNTH5
FRLNTH4
FRLNTH3
FRLNTH2
FRLNTH1
FRLNTH0
Default Value
0
1
0
1
Clock Control 3 Register Definition
BIT
Register Name
R/W
bit 0
~
bit 7
FRLNTH0
FRLNTH7
Frame to Line Threshold Level
Control bit
R/W
The threshold parameter from Frame-Lock clock
mode to Line-Lock clock mode.
Definition
CLOCK CONTROL-4 REGISTER ( R / W ) [ SUB ADDRESS : 0x39 ]
This register controls the Clock Transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select Control
2 Register ( 0x09 ).
Sub Address 0x39
Default Value : 0xDC
bit 7
bit 6
bit 4
bit 3
bit 2
bit 1
bit 0
FRFXTH7
FRFXTH6
FRFXTH5
FRFXTH4
FRFXTH3
FRFXTH2
FRFXTH1
FRFXTH0
Default Value
1
0
1
0
bit 5
Clock Control 4 Register Definition
BIT
Register Name
R/W
Definition
bit 0
~
FRFXTH0
bit 7
FRFXTH7
Frame to Fix Clock Threshold
Level Control bit
R/W
The threshold parameter from Frame-Lock clock
mode to Fixed clock mode.
CLOCK CONTROL-5 REGISTER ( R / W ) [ SUB ADDRESS 0x3A ]
This register controls the Clock Transition time in clock Auto Mode set by ( bit 7 : bit 6 ) of the Auto Select Control 2
Register ( 0x09 ).
Sub Address 0x3A
Default Value : 0x04
bit 7
bit 6
bit 4
bit 3
bit 2
bit 1
bit 0
FXLNTH6
FXLNTH5
FXLNTH4
FXLNTH2
FXLNTH1
FXLNTH0
Default Value
0
1
0
bit 5
FXLNTH7
FXLNTH3
Clock Control 5 Register Definition
BIT
Register Name
R/W
Definition
bit 0
~
bit 7
FXLNTH0
FXLNTH7
Fix Clock to Line Threshold
Level Control bit
R/W
The threshold parameter for switching between
the Fixed clock and Line-Lock clock modes.
Rev.0
93
2003/01
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