參數(shù)資料
型號(hào)： AK8850
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： NTSC Digital Video Decoder
中文描述： NTSC制式數(shù)字視頻解碼器
文件頁(yè)數(shù)： 35/99頁(yè)
文件大?。?/td> 1757K
代理商： AK8850
ASAHI KASEI
[AK8850]
7-2-4 CLOCK MODES
The AK8850 operates under the following 3 clock modes.
(1) LINE-LOCKED CLOCK MODE
A high quality input signal from a Signal generator or DVD can be used and the corresponding Horizontal Sync Signal
( HSYNC ) can be extracted. A clock generated in this way is called Line-Locked Clock. Even if the Line-Locked Clock
mode is selected, it is possible for the chip to be forced into Fixed–Clock mode, depending upon the input signal quality
(poor or no-input signal conditions).
( 2 ) FRAME-LOCKED CLOCK MODE
The Vertical Sync Signal in the input signal is used to generate a clock when skew exists in the input signal, as in the
case of a VCR. A clock generated in this way is called Frame-Locked Clock. Even if the Frame-Locked Clock mode is
selected, there is a case to be forced to the Fixed-Clock mode which is depending on the input signal quality ( poor or
no- input signal conditions).
( 3 ) FIXED-CLOCK MODE
A clock not affected by PLL control.
( 4 ) CLOCK AUTO TRANSITION MODE ( default mode )
Depending on the characteristics of the input signal, the clock mode is automatically selected. When the auto select
mode is enabled, the AK8850 automatically shifts its clock mode from / to Line-Clocked mode to / from Frame-Locked
mode then to Fixed-Clock mode until it selects the optimum mode.
Since an input- signal-synchronized clock can be generated in both the Line-Locked Clock and Frame-Locked Clock
modes, ITU-R BT.656 compatible output is available if the input signal quality is good enough.
In Fixed Clock mode operation, the AK8850’s PLL is disabled. This clock mode is usually selected when the input signal
quality is poor and the Auto Clock mode is set by Clock Mode Register. In this mode, the input clock must be
synchronized with the input signal so that output data remains compatible with ITU-R BT.656 specifications.
An external VCXO clock circuit connection is shown below.
The AK8850 internally switches the Line and
the Frame-Locked Loop Filter outputs, and adds
the V-I converted current and the internal current
DAC output together, then it outputs this value
on the IVCXO pin. By connecting an external
resistor to this pin, a control voltage to the
external VCXO is provided. A voltage to control
the oscillating center frequency of the VCXO is
adjustable by setting the above-mentioned
current DAC input code, using the PLL-DAC
Code Set Register ( address : 0x47 ). In this
case, adjusting the external VCXO oscillating
center frequency is accomplished by selecting
the
Fixed
Clock
mode
[
CONTROL
2
REGISTER ].
FLPF
LLPF
CLK
IVCXO
Internal Clock
10K
DAC
LINE PLL
CIRCUIT
PLL BLOCK DIAGRAM
Gm
27MHz
VCXO
C2
F
C1
F
R
F
LPF SW
FRAME PLL
CIRCUIT
AK8850
C2
L
C1
L
R
L
Clock Control Register Description :
Clock mode is controlled by the [ CONTROL
* [ CONTROL 2 REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CLKMODE1
CLKMODE0
ACC1
ACC0
DPCC1
DPCC0
DPCT1
DPCT0
Default Value
1
0
1
Rev.0
40
2002/01
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