參數(shù)資料
型號(hào)： AK8850
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： NTSC Digital Video Decoder
中文描述： NTSC制式數(shù)字視頻解碼器
文件頁數(shù)： 24/99頁
文件大?。?/td> 1757K
代理商： AK8850
ASAHI KASEI
[AK8850]
( 1-2 ) PEDESTAL CLAMP TIMING PULSE
The AK8850’s Clamp point is initially set to the SYNC-TIP level. It is possible to clamp it at the Pedestal point by
changing a register value.
The Start point of the Pedestal clamp timing pulse is set by [ PCLPSTAT 2 : PCLPSTAT 0 ]-bit of the [ CLAMP TIMING
2 CONTROL REGISTER] as shown below.
The Clamp period ( pulse width ) is set by [ PCLPWIDTH3 : PCLPWIDTH 0]-bit of the [ CLAMP TIMING 2 CONTROL
REGISTER ].
SYNC-SEPARATION RELATED REGISTER DESCRIPTION.
During the SERRATION pulse period, if no SYNCDET falling edge is detected before the start position set by
[ PCLPSTA2 : PCLSTA0]-bit, the Pedestal clamp timing pulse is not generated. This avoids mis-clamping of Serration
pulse input.
* Operation with typical video input signal
* Operation with Serration pulse input signal
at HSYNC Input
Video Signal In
Loacation of HSYNC
(AIN1/AIN2/AIN3)
1Clock = 37nsec
After LPF
SYNC1/2/3 Input
HSYNC
R=620
C=510pF
LPF
380nsec
70mV
After Sync Separation
Internal Sync Reference
(SYNCDET)
2+[PCLPSTA3: PCLPSTA0]-bit [clks]
[PCLPWIDTH3: PCLPWIDTH0]-bit Clocks
Pedestal Clamp
Timing pulse
at Serration pulse Input
After Sync Separation
Internal Sync Reference
(SYNCDET)
Pedestal Clamp
Timing pulse
After LPF
SYNC1/2/3Input
Serration pulse
2+[PCLPSTA3: PCLPSTA0]-bit [clks]
Rev.0
30
2002/01
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