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參數(shù)資料
| 型號： | AK8850 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | NTSC Digital Video Decoder |
| 中文描述： | NTSC制式數(shù)字視頻解碼器 |
| 文件頁數(shù)： | 26/99頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | AK8850 |
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ASAHI KASEI
[AK8850]
( 1-6-1 ) CLAMP TIMING PULSE SOURCE SET
Input clamp setting is done via the [ CLAMP CONTROL REGISTER ].
[Clamp Control Register]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
UNMASK
Reserved
ACLAMP
INCLPTMG
FBCLPTMG1
FBCLPTMG0
CLPLVL1
CLPLVL0
Default Value
0
[ INCLPTMG]-bit sets the clamp timing pulse of the input clamp.
INCLPTMG-bit (bit-4)
Clamp timing pulse Generation
0
Clamp timing pulse generated by Internal Clamp pulse generator
1
Clamp timing pulse from EXTCLP pin
[ FBCLPTMG1 : FBCLPTMG0]-bit sets the clamp position and the clamp source.
[FBCLPTMG1:FBCLPTMG0]-bit
(bit-3:bit-2)
Clamp timing pulse
00
Video signal is clamped at synctip level with internal Clamp timing pulse (Default)
01
Video signal is clamped at synctip level with External Clamp timing pulse
10
Video signal is clamped at pedestal level with internal Clamp timing pulse
11
Reserved
Combinations of INCLPTMG-bit, the [FBCLPTMG1 : FBCLPTMG0 ]-bit and input / output setting of the EXTCLP pin in
various modes are shown in the following table. Some combinations are”Prohibited” as shown in the table, and
therefore should not be selected ( otherwise internal timing has priority ).
Internal clamp timing monitoring is described below..
[
FBCLPTMG1:FBCLPTMG0]-bit
Synctip Clamp
FBCLPTMG1=0
Pedestal Clamp
FBCLPTMG1 =1
Internal Timing
FBCLPTMG0=0
External Timing
FBCLPTMG0=1
Internal Timing
FBCLPTMG0=0
External Timing
FBCLPTMG0=1
0
(Internal Timing)
EXTCLP = OUTPUT
Synctip Clamp
Prohibit
EXTCLP = OUTPUT
Pedestal
EXTCLP = INPUT
Pedestal clamp
INCLPTMG-bit
1
(External
Timing)
Prohibit
EXTCLP =INPUT
Synctip Clamp
EXTCLP = INPUT
Pedestal Clamp
Prohibit
( 1-6-2 ) INTERNAL CLAMP TIMING MONITORING FUNCTION VIA EXTCLP PIN
It is possible to monitor the clamp timing pulse on EXTCLP pin. This is enabled by the [ EXTMON1 : EXTMON0 ]-bit of
the [ CLAMP TIMING1 CONTROL REGISTER ].
The timing pulse monitor function is disabled when the external clamp pulse input is selected.
* [ CLAMP TIMING 1 CONTROL REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EXTMON1
EXTMON0
SCLPWIDTH2
SCLPWIDTH1
SCLPWIDTH0
SCLPSTAT2
SCLPSTAT1
SCLPSTAT0
Default Value
0
Monitoring of clamp timing is possible by setting [ INCLPTMG : FBCLPTMG 1 : FBCLPTMG 0 ]-bit.
[INCLPTMG: FBCLPTMG1:FBCLPTMG0]-bit
Monitor with EXTCLP pin
Note
[000]
possible
Synctip Clamp
[010]
possible
Pedestal Clamp
Rev.0
32
2002/01
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