參數(shù)資料
型號(hào): AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁(yè)數(shù): 30/99頁(yè)
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
The Pedestal clamp timing pulse at the default state generates a clamp pulse as shown in the following timing diagram.
Video signal Input
Position of HSYNC
(AIN1/AIN2/AIN3)
1Clock = 37nsec
After LPF
SYNC1/2/3 input
HSYNC
380nsec
70mV
After Sync Separation
Internal Sync Reference
(SYNCDET)
[PCLPSTA3: PCLPSTA0]-bit Clocks
[PCLPWIDTH3: PCLPWIDTH0]-bit Clocks
Pedestal clamp
timing pulse
5.3usec
4.92usec=133[clk]
( Default 5.48usec = 148 [clk] )
Default value is 21 cycles
2.5usec
Default Pedestal clamp timing
( 1-6-5 ) CLAMP TIMING PULSE MASK FUNCTION
The Clamp timing pulse generation is masked at the default state to avoid mis-clamping outside the SYNC signal timing.
This masking function can be disabled.
* [ CLAMP CONTROL REGISTER ] set is done by UNMASK-bit
UNMASK-bit
Function
0
Masked
default
1
Un-Masked
For typical use,please set UNMASK bit =0.
Rev.0
36
2002/01
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