參數(shù)資料
型號: AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 76/99頁
文件大小: 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
CLAMP TIMING 1 CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x0B ]
This register sets SYNC-TIP Clamp timing. Clamp Timing Pulse generation and its pulse width can be adjusted.
Output signal mode selection of the EXTCLP pin is also possible. For a timing diagram, refer to the SYNC Separation
description in the Clamp section. Reserved bits must be set to “ 0 “.
Sub Address 0x0B
Default Value : 0x11
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EXTCLP1
EXTCLP0
SCLPWIDTH2
SCLPWIDTH1
SCLPWIDTH0
SCLPSTAT2
SCLPSTAT1
SCLPSTAT0
Default Value
0
1
0
1
Clamp Timing Control Register
BIT
Register Name
R/W
Definition
Setting the start position of synctip clamp pulse
bit 0
SCLPSTAT0
SCLPSTAT2
default value is
SCLPSTA2 : SCLPSTA0 = 001
[SCLPSTAT2 SCLPSTAT0 ]
000 : 2clks later
001 : 4clks later
011 : 8clks later
100 : 10clks later
101 : 12clks later
111 : 16clks later
1clk is about 37[nsec]
R/W
Synctip Clamp Start timing0
Synctip Clamp Start timing2 bit
bit 2
010 : 6clks later
110 : 14clks later
SCLPWIDTH0
Synctip Clamp Pulse Width0 bit
Synctip Clamp Pulse Width2 bit
R/W
SCLPWIDTH2 : SCLPWIDTH0 = 010.
[SCLPWIDTH3 SCLPWIDTH0]
001 : 4 clks (148nsec)
010 : 8 clks (296nsec)
011 : 16 clks (592nsec)
100 : 24 clks (888nsec)
101 : 32 clks (1.18usec)
110 : 40 clks (1.48usec)
111 :48 clks (1.78usec)
Setting the synctip clamp pulse width
Default value is
bit 3
SCLPWIDTH2
bit 5
000 : 2 clks (74nsec)
bit 6
Setting the output the timing data from
EXTCLP-pin.
00 : Hi-Z (Defaul)
11 : SYNCDET signal
R/W
External Clamp 0 bit
EXTCLP0
External Clamp 1 bit
EXTCLP1
bit 7
[EXTCLP1:EXTCLP0]
01 : Internal synctip clamp timing pulse.
10 : Internal pedestal clamp timing pulse.
Rev.0
78
2003/01
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