參數(shù)資料
型號(hào): AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁(yè)數(shù): 28/99頁(yè)
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
* SYNC-TIP clamp pulse width set by [ SCLPWIDTH2 : SCLPWIDTH0 ]-bit
[SCLPWIDTH2: SCLPWIDTH0]-bit
Pulse width
000
2-Clocks (74nsec)
001
4-Clocks (148nsec)
010
8-Clocks (296nsec) (Default)
011
16-Clocks (592usec)
100
24-Clocks (888nsec)
101
32-Clocls (1.18usec)
110
40-Clocks (1.48usec)
111
48-Clocks (1.78usec)
SYNC-TIP clamp pulse width is set using the [ SCLPWIDTH2 : SCLPWIDTH0 ]-bit = [010], with ( 8 clocks = 296 ns) as
the default value. Clamp pulse width can be adjusted using the [ PCLPWIDTH3 : PCLDWIDTH0 ]-bit as shown below.
* [ CLAMP TIMING2 CONTROL REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SLCLV1
SLCLV0
PCLPWIDTH2
PCLPWIDTH1
PCLPWIDTH0
PSCLPSTAT2
PCLPSTAT1
PCLPSTAT0
Default Value
0
1
0
Please use SLCLV1 : SLCLV0 to adjust the SYNC-TIP slice position.
[SLCLV1: SLCLV0]-bit
Slice Level
00
Sliced at the position from about 70mV over synctip.
01
Sliced at the position from about 140mV over synctip.
10
Invalid setting
11
Sliced at the position from about 105mV over synctip.
The default SYNC-TIP clamp timing pulse generates a clamp pulse as shown in the following timing diagram.
Video Input
Sync position
(AIN1/AIN2/AIN3)
1Clock = 37nsec
after LPF
SYNC1/2/3 input
HSYNC
R=620
C=510pF
LPF
380nsec
2[clks] + 2[clks] = 4[clks] (148[nsec])
Synctip Clamp
timing pulse
296 [nsec]
380[nsec] + 148[nsec] = 528[nsec]
70mV(Default
After Sync Separation
Internal Sync Reference
(SYNCDET)
824 [nsec]
Default Synctip Clamp Timing
Rev.0
34
2002/01
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