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參數(shù)資料
| 型號(hào)： | AK8850 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | NTSC Digital Video Decoder |
| 中文描述： | NTSC制式數(shù)字視頻解碼器 |
| 文件頁(yè)數(shù)： | 61/99頁(yè) |
| 文件大?。?/td> | 1757K |
| 代理商： | AK8850 |
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ASAHI KASEI
[AK8850]
* [ OUTPUT CONTROL REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VDVSYNC
FFDELAY
HALFCLK
FRAME
DVALVLK
FEILD
VSYNC
HSYNC
Default Value
0
1
0
1
0
Logical state can be altered by these registers. Default value is “ 0 “ as shown in the timing diagram.
* [ CONTROL 1 REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FRCSYNC
DECIMAT
INTPOL1
INTPOL0
AGCC1
AGCC0
AGCT1
AGCT0
Default Value
1
0
FRCSYNC-bit controls output on FRAME 1 pin.
7-4-20 VLOCK FUNCTION
The AK8850 synchronizes its internal operation with the input signal’s FRAME configuration. For example, if the input
signal Frame configuration consists of 525 lines, the internal operation uses the 525 Line configuration. This is called the
VLOCK configuration.
When the input signal configured with 525 Line per Frame is switched to 524 Lines, the operation tracks to the switched
input signal system.
In this case VLOCK function is put into un-locked state during the tracking time. The un-locked state is verified by the
[ STATUS 1 REGISTER ].
VLOCK status is observed on the DVALID pin by setting the DVAL / VLK-bit of the [ OUTPUT CONTROL REGISTER ] ( R
/ W ) [ SUB ADDRESS 0x05 ].
VLOCK Status
Status 1 Register
VLOCK-bit
VLOCK output pin
Locked (synchronaize with Input video signal)
1
High
UnLocked Un-synchronaized with input video signal
0
Low
The transition timing of the VLOCK output pin changes with VLOCK configuration conditions. .
Rev.0
64
2003/01
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相關(guān)代理商/技術(shù)參數(shù) |
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| AK8853VN | 制造商:AKM 制造商全稱:AKM 功能描述:NTSC/PAL/SECAM Digital Video Decoder |
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