參數(shù)資料
型號(hào)： 935268625551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 69/82頁
文件大?。?/td> 1965K
代理商： 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
71 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Interlock time is the time allowed between an action by one agent and the following action by the other agent. An agent can be a sender
or a receiver. Interlocking actions require a response signal from the other agent before processing can continue.
15. Application information
td9
ready to nal strobe edge delay
-
75
-
60
-
50
ns
td10
DACK off to IORDY high-Z delay
-
20
-
20
-
20
ns
td11
DACK on to IORDY HIGH delay
0-0-0-
ns
td12
nal strobe edge to DREQ off or DIOW
on delay
50
-
50
-
50
-
ns
td13
rst strobe delay after control signal on
0
230
0
200
0
170
ns
Table 81:
UDMA mode timing parameters…continued
VCC = 4.0 to 5.5 V; VGND =0V; Tamb = 40 to +85 °C.
Symbol
Parameter
Mode 0
Mode 1
Mode 2
Unit
Min
Max
Min
Max
Min
Max
Fig 36. Typical interface connections for Generic Processor mode.
Fig 37. Typical interface connections for Split Bus mode (slave mode).
MGT515
data
read strobe
16
ISP1581
CPU
DATA15 to DATA0
(R/W)/RD
address
8
AD7 to AD0
write strobe
DS/WR
chip select
CS
8
MGT516
DATA[15:0]
DREQ
ISP1581
DMA
8051
MICROCONTROLLER
AD7 to
AD0
INT
ALE/A0
P0.7/AD7
to
P0.0/AD0
ALE
DACK
DIOW
DIOR
write
strobe
read
strobe
interrupt
address
latch
enable
address/data
(R/W)/RD
DS/WR
RD
INTn
WR
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