參數(shù)資料
型號(hào): 935268625551
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 38/82頁(yè)
文件大?。?/td> 1965K
代理商: 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
43 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.5.2
Chip ID register (address: 70H)
This read-only register contains the chip identication and the hardware version
numbers. The rmware should check this information to determine the functions and
features supported. The register contains 3 bytes and the bit allocation is shown in
9
reserved
reserved.
8
EP0SETUP
A logic 1 indicates that a SETUP token was received on
Endpoint 0.
7
reserved
reserved.
6
DMA
DMA status: A logic 1 indicates a change in the DMA Status
register.
5
HS_STAT
High Speed Status:.A logic 1 indicates a change from FS to
HS mode (HS connection). This bit is not set, when the system
goes into a FS suspend.
4
RESUME
Resume status: A logic 1 indicates that a status change from
‘suspend’ to ‘resume’ (active) was detected.
3
SUSP
Suspend status: A logic 1 indicates that a status change from
active to ‘suspend’ was detected on the bus.
2
PSOF
Pseudo SOF interrupt: A logic 1 indicates that a Pseudo SOF
or
SOF was received. Pseudo SOF is an internally generated
clock signal (FS: 1 ms period, HS: 125
s period) synchronized
to the USB bus SOF/
SOF.
1
SOF
SOF interrupt: A logic 1 indicates that a SOF/
SOF was
received.
0
BRESET
Bus Reset: A logic 1 indicates that a USB bus reset was
detected.
Table 58:
Interrupt register: bit description…continued
Bit
Symbol
Description
Table 59:
Chip ID register: bit allocation
Bit
23
22
21
20
19
18
17
16
Symbol
CHIPID[23:16]
Reset
15H
Bus reset
15H
Access
R
Bit
15
14
13
12
11
10
9
8
Symbol
CHIPID[15:8]
Reset
81H
Bus reset
81H
Access
R
Bit
7
6
5
4
3
2
1
0
Symbol
VERSION[7:0]
Reset
51H
Bus reset
51H
Access
R
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