參數(shù)資料
型號(hào)： 935268625551
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 19/82頁(yè)
文件大?。?/td> 1965K
代理商： 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
26 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.3.6
Endpoint Type register (address: 08H)
This register sets the Endpoint type of the indexed endpoint: isochronous, bulk or
interrupt. It also serves to enable the endpoint and congure it for double buffering.
Automatic generation of an empty packet for a zero length TX buffer can be disabled
via bit NOEMPKT. The register contains 2 bytes and the bit allocation is shown in
9.3.7
Short Packet register (address: 24H)
This register is reserved.
Table 24:
Endpoint Type register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
--------
Bus reset
--------
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
NOEMPKT
ENABLE
DBLBUF
ENDPTYP[1:0]
Reset
---
0
00H
Bus reset
---
0
00H
Access
R/W
Table 25:
Endpoint Type register: bit description
Bit
Symbol
Description
15 to 5
reserved
reserved.
4
NOEMPKT
No Empty Packet: A logic 0 causes an empty packet to be
appended to the next IN token of the USB data, if the Buffer
Length register or the Endpoint MaxPacketSize register is zero.
A logic 1 disables this function. This bit is applicable only in
DMA mode.
3
ENABLE
Endpoint Enable: A logic 1 enables the FIFO of the indexed
endpoint. The memory size is allocated as specied in the
Endpoint MaxPacketSize register. A logic 0 disables the FIFO.
Note: ‘Stalling’ a data endpoint will confuse the Data Toggle bit
on the stalled endpoint because the internal logic picks up from
where it has stalled. Therefore, the Data Toggle bit must be
reset by disabling and re-enabling the corresponding endpoint
(by setting the bit ‘ENABLE’ to 0 or 1 in the endpoint type
register) to reset the PID.
2
DBLBUF
Double Buffering: A logic 1 enables double buffering for the
indexed endpoint. A logic 0 disables double buffering.
1 to 0
ENDPTYP[1:0]
Endpoint Type: These bits select the endpoint type as follows:
01H — isochronous
02H — bulk
03H — interrupt.
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