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參數(shù)資料
| 型號(hào)： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 45/82頁(yè) |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
5 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.2 Pin description
Table 2:
Pin description for LQFP64
Symbol[1]
Pin
Type[2]
Description
DGND
1
-
digital ground
VCC(5.0)[3]
2
-
supply voltage (3.3 or 5.0 V)
for 5.0 V operation, this is the only pin used. Refer to
AGND
3
-
analog ground
4
-
regulated supply voltage (3.3 V
± 0.3 V) from internal
regulator; supplies internal analog circuits; used to connect
decoupling capacitor and 1.5 k
pull-up resistor on D+ line
Remark: Cannot be used to supply external devices. Refer
to Section 10
D
5
A
USB D
connection (analog)
D
+
6
A
USB D
+ connection (analog)
RPU
7
A
connection for external pull-up resistor for USB D
+ line;
must be connected to VCCA(3.3) via a 1.5 k resistor
RREF
8
A
connection for external bias resistor; must be connected to
ground via a 12.0 k
(± 1%) resistor
MODE1
9
I
selects function of pin ALE/A0 (in Split Bus mode only):
0 — ALE function (address latch enable)
1 — A0 function (address/data indicator).
Remark: Connect to VCC(5.0) in the Generic Processor
mode.
input pad; TTL; 5 V tolerant; internal pull-down resistor.
RESET
10
I
reset input; a LOW level produces an asynchronous reset;
connect to VCC for power-on reset (internal POR circuit)
TTL with hysteresis; 5 V tolerant; internal pull-up resistor.
EOT
11
I
End Of Transfer input (programmable polarity, see
Table 37); used in DMA slave mode only
input pad; TTL; 5 V tolerant; 5 ns slew rate control.
DREQ
12
I/O
DMA request (programmable polarity); direction depends
on the bit MASTER in the DMA Hardware register (DMA
master: input, DMA slave: output); see Table 35 and
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
DACK
13
I/O
DMA acknowledge (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 35 and
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
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