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參數(shù)資料
| 型號： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 67/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
7 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
READY/
IORDY
22
I/O
Generic processor mode: ready signal (READY; output)
A LOW level signals that ISP1581 is processing a previous
command or data and is not ready for the next command or
data transfer; a HIGH level signals that ISP1581 is ready
for the next microprocessor read or write.
Split Bus mode: DMA ready signal (IORDY; input); used
for accessing ATA/ATAPI peripherals (PIO and UDMA
modes only).
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
DGND
23
-
digital ground
VCC(3.3)[3]
24
-
supply voltage (3.3 V
± 0.3 V); supplies internal digital
circuits or it is the tapped out voltage from the internal
regulator; this regulated voltage cannot be used to drive
external devices; see Section 10
CS
25
I
chip select input; TTL; 5 V tolerant.
(R/W)/RD
26
I
input; function is determined by input MODE0 at power-up:
MODE0 = 0 — pin functions as R/W (Motorola style)
MODE0 = 1 — pin functions as RD (8051 style).
input pad; TTL with hysteresis; 5 V tolerant.
DS/WR
27
I
input; function is determined by input MODE0 at power-up:
MODE0 = 0 — pin functions as DS (Motorola style)
MODE0 = 1 — pin functions as WR (8051 style).
input pad; TTL with hysteresis; 5 V tolerant.
INT
28
O
interrupt output; programmable polarity (active HIGH or
LOW) and signaling (edge or level triggered)
CMOS output; 5 ns slew rate control.
ALE/A0
29
I
input; function determined by input MODE1 during
power-up:
MODE1 = 0 — pin functions as ALE (address latch
enable); a falling edge latches the address on the
multiplexed address/data bus (AD[7:0])
MODE1 = 1 — pin functions as A0 (address/data selection
on AD[7:0]); a logic 1 detected on the rising edge of the
WR pulse qualies AD[7:0] as a register address; a logic 0
detected on the rising edge of the WR pulse qualies
AD[7:0] as a register data; used in Split Bus mode only.
Remark: Connect to DGND in the Generic Processor
mode.
input pad; TTL; 5 V tolerant.
AD0
30
I/O
bit 0 of multiplexed address/data.
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
Table 2:
Pin description for LQFP64 …continued
Symbol[1]
Pin
Type[2]
Description
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