參數(shù)資料
型號(hào)： 935268625551
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 36/82頁(yè)
文件大小： 1965K
代理商： 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
41 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.4.9
DMA Endpoint register (address: 58H)
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in Table 55.
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (02CH) at any time. Doing so would result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint.
However, if the DMA Endpoint register is pointed to an active endpoint, the rmware
must not reference the same endpoint on the Endpoint Index register.
9.5 General registers
9.5.1
Interrupt register (address: 18H)
The Interrupt register consists of 4 bytes. The bit allocation is given in Table 57.
When a bit is set in the Interrupt register, this indicates that the hardware condition for
an interrupt has occurred. When the Interrupt register content is non-zero, the INT
output will be asserted. Upon detecting the interrupt, the external microprocessor
must read the Interrupt register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition,
various bus states can generate an interrupt: Resume, Suspend, Pseudo-SOF, SOF
and Bus Reset. The DMA Controller only has one interrupt bit: the source for a DMA
interrupt is shown in the DMA Interrupt Reason register (see Table 51).
Each interrupt bit can be individually cleared by writing a logic 1. The DMA interrupt
bit can be cleared by writing a logic 1 to the related interrupt source bit in the DMA
Interrupt Reason register and writing a logic 1 to the DMA bit of the interrupt register.
Bit
7
6
5
4
3
2
1
0
Symbol
IE_1F0_
WF_E
IE_1F0_
WF_F
IE_1F0_
RF_E
IE_
READ_1F0
IE_BSY_
DONE
IE_TF_
RD_DONE
IE_CMD_
INTRQ_OK
reserved
Reset
0000000
-
Bus reset
0000000
-
Access
R/W
Table 55:
DMA Endpoint register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
EPIDX[2:0]
DMADIR
Power Reset
----
0000
Bus Reset
----
0000
Access
R/W
Table 56:
DMA Endpoint register: bit description
Bit
Symbol
Description
7 to 4
-
reserved
3 to 1
EPIDX[2:0]
selects the indicated endpoint for DMA access
0
DMADIR
0 — selects the RX/OUT FIFO for DMA read transfers
1 — selects the TX/IN FIFO for DMA write transfers.
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