- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24828 > 935268625551 (NXP SEMICONDUCTORS) UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 27/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625551 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
33 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 34:
DMA Conguration register: bit description
Bit
Symbol
Description
15
-
reserved
14
IGNORE_IORDY
A logic 1 ignores the IORDY input signal (UDMA mode only).
13
ATA_MODE
A logic 1 congures the DMA core for ATA or MDMA mode.
Used when issuing DMA commands 02H to 07H, 0AH and
0CH; also used when directly accessing task le registers.
A logic 0 congures the DMA core for non-ATA mode. Used
when issuing DMA commands 00H and 01H.
12 to 11 DMA_MODE[1:0]
These bits affect the timing for UDMA and MDMA mode:
00H — UDMA/MDMA mode 0: ATA(PI) compatible timings
01H — UDMA/MDMA mode 1: ATA(PI) compatible timings
02H — UDMA/MDMA mode 2: ATA(PI) compatible timings
03H — MDMA mode 3: enables the DMA Strobe Timing
durations; only used in MDMA mode.
10 to 8
PIO_MODE[2:0][3]
These bits affect the PIO timing (see Table 78):
00H to 04H — PIO mode 0 to 4: ATA(PI) compatible timings
05H to 07H — reserved.
7
DIS_XFER_CNT
A logic 1 disables the DMA Transfer Counter (see Table 31).
The transfer counter can only be disabled in GDMA slave
mode; in master mode the counter is always enabled.
6 to 4
BURST[2:0]
These bits select the DMA burst length and the DREQ timing
(GDMA Slave mode only):
00H — DREQ is asserted until the last byte/word is
transferred or until the FIFO becomes full or empty
01H — DREQ is asserted and negated for each byte/word
transferred[1][2]
02H — DREQ is asserted and negated for every
2 bytes/words transferred[1][2]
03H — DREQ is asserted and negated for every
4 bytes/words transferred[1][2]
04H — DREQ is asserted and negated for every
8 bytes/words transferred[1][2]
05H — DREQ is asserted and negated for every
12 bytes/words transferred[1][2]
06H — DREQ is asserted and negated for every
16 bytes/words transferred[1][2]
07H — DREQ is asserted and negated for every
32 bytes/words transferred[1][2].
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 080207R0 | TELEFON-AKKU |
| 080216R0 | TELEFON-AKKU |
| 080219R0 | TELEFON-AKKU |
| 080251R0 | TELEFON-AKKU |
| 935268664112 | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
| 935269544557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3 |
| 935269987557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557 |
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。