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| 型號(hào)： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 25/82頁(yè) |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
31 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
PIO Read or Write that started using DMA Command Register only performs 16-bit transfer.
9.4.2
DMA Transfer Counter register (address: 34H)
This 4-byte register is used to set up the total byte count of a DMA transfer (DMACR).
It indicates the remaining number of bytes left for transfer. The bit allocation is given
in Table 31.
The transfer counter is used in DMA modes: PIO (commands: 04H, 05H), UDMA
(commands: 02H, 03H), MDMA (commands: 06H, 07H) and GDMA (commands:
00H, 01H).
A new value is written into the register starting with the lower byte (DMACR1) or the
lower word (MSByte: DMACR2, LSByte: DMACR1). Internally, the transfer counter is
initialized only after the last byte (DMACR4) has been written.
In the GDMA Slave mode only, the transfer counter can be disabled via bit
DIS_XFER_CNT in the DMA Conguration Register (see Table 33). In this case,
input signal EOT can be used to terminate the DMA transfer when data is transferred
from the external device to the host via IN tokens. The last packet in the FIFO is
validated when pin EOT is asserted.
11
Reset DMA
Reset DMA: Initializes the DMA core to its power-on
reset state.
Remark: When the DMA core is reset during the Reset
DMA command, the DREQ, DACK, DIOW and DIOR
handshake pins will be temporarily asserted. This can
cause some confusion to the external DMA Controller.
To prevent this from happening, start the external DMA
Controller only after the DMA reset is done.
12
MDMA stop
MDMA stop: This command immediately stops the
MDMA data transfer. This is applicable for commands
06H and 07H only.
13 to FF
-
reserved
Table 30:
DMA commands…continued
Code (Hex)
Name
Description
Table 31:
DMA Transfer Counter register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
DMACR4 = DMACR[31:24]
Reset
00H
Bus reset
00H
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
DMACR3 = DMACR[23:16]
Reset
00H
Bus reset
00H
Access
R/W
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