Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
39 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.4.7
DMA Interrupt Reason register (address: 50H)
This 2-byte register shows the source(s) of a DMA interrupt. Each bit is refreshed
after a DMA command has been executed. An interrupt source is cleared by writing a
logic 1 to the corresponding bit. The bit allocation is given in
Table 51.Table 49:
Task File register 3F6 (address: 4EH): bit allocation
CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = L.
Bit
7
6
5
4
3
2
1
0
Symbol
alternate status/command (ATA or ATAPI)
Reset
00H
Bus reset
00H
Access
R/W
Table 50:
Task File register 3F7 (address: 4FH): bit allocation
CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = H.
Bit
7
6
5
4
3
2
1
0
Symbol
drive address (ATA) or reserved (ATAPI)
Reset
00H
Bus reset
00H
Access
R/W
Table 51:
DMA Interrupt Reason register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
ODD_IND
EXT_EOT
INT_EOT
INTRQ_
PENDING
DMA_
XFER_OK
Reset
-
00000
Bus reset
-
00000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
1F0_WF_E
1F0_WF_F
1F0_RF_E
READ_1F0
BSY_
DONE
TF_RD_
DONE
CMD_
INTRQ_OK
reserved
Reset
0000000
-
Bus reset
0000000
-
Access
R/W
Table 52:
DMA Interrupt Reason Register: bit description
Bit
Symbol
Description
15 to 13 -
reserved
12
ODD_IND
A logic 1 indicates that the last packet with odd bytes has
been transferred from the OUT token buffer to the DMA. This
is applicable only for the OUT token data in the DMA slave
mode. It has no meaning for the IN token data. Refer to the
document
Using the Odd Bit Indicator for DMA.
11
EXT_EOT
A logic 1 indicates that an external EOT is detected. This is
applicable only in GDMA slave mode.
10
INT_EOT
A logic 1 indicates that an internal EOT is detected. see