參數(shù)資料
型號: 935268625551
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 68/82頁
文件大?。?/td> 1965K
代理商: 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
70 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
(1) Programmable polarity: shown as active LOW.
Fig 35. UDMA timing: host terminating a burst during a write command.
DREQ (drive)
DACK(1) (host)
DIOR (host)
DIOW (host)
DATA [15:0] (host)
DA [2:0] and CS [1:0]
IORDY (drive)
td2
td3
td2
th3
tsu1
th1
CRC
th3
td10
MGT514
td12
Table 81:
UDMA mode timing parameters
VCC = 4.0 to 5.5 V; VGND =0V; Tamb = 40 to +85 °C.
Symbol
Parameter
Mode 0
Mode 1
Mode 2
Unit
Min
Max
Min
Max
Min
Max
Tcy1
read/write cycle time (from strobe edge
to strobe edge)
114
-
75
-
55
-
ns
tsu2
data set-up time at receiver
15
-
10
-
7
-
ns
th2
data hold time at receiver
5-5-5-
ns
tsu1
data set-up time at sender
70
-
48
-
34
-
ns
th1
data hold time at sender
6-6-6-
ns
td1
unlimited interlock time[1]
0-0-0-
ns
td2
limited interlock time[1]
0
150
0
150
0
150
ns
td3
limited interlock time with minimum[1]
20
-
20
-
20
-
ns
td4
data line drivers switch-off delay
-
10
-
10
-
10
ns
td5
data line drivers switch-on delay (host)
20
-
20
-
20
-
ns
data line drivers switch-on delay (drive)
0-0-0-
ns
tsu3
control signal set-up time before DACK
on
20
-
20
-
20
-
ns
th3
control signal hold time after DACK off
20
-
20
-
20
-
ns
td6
DACK on to control signal transition delay
20
70
20
70
20
70
ns
td7
ready to paused delay
160
-
125
-
100
-
ns
td8
strobe to ready delay to ensure a
synchronous pause
-50-30
-20
ns
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