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| 型號(hào)： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 59/82頁(yè) |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
DREQ is continuously asserted until the last transfer is done or the FIFO is full.
Data strobe: DACK (read/write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 20. GDMA slave mode timing (BURST = 00H, MODE = 02H).
th1
tw1
tsu1
td1
tsu2
td2
th2
Tcy1
(write) DATA[15:0]
(read) DATA[15:0]
DREQ (2)
HIGH
DACK(1)
DIOR/DIOW(1)
MGT501
tw2
th3
DREQ is asserted for every transfer.
Data strobes: DIOR (read), DIOW (write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 21. GDMA slave mode timing (BURST = 01H, MODE = 00H).
td1
tw1
tsu1
th1
tsu2
td2
th2
Tcy1
(write) DATA[15:0]
(read) DATA[15:0]
DREQ (2)
DACK(1)
DIOR/DIOW(1)
MGT502
tsu3
ta1
th3
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