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參數(shù)資料
| 型號： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 58/82頁 |
| 文件大小： | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
61 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Tcy1 is the total cycle time, consisting of the command active time tw1and is the command recovery (= inactive) time tw2:Tcy1 =tw1 +tw2.
The minimum timing requirements for Tcy1, tw1 and tw2 must all be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a
host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY
DEVICE data. A device implementation shall support any legal host implementation.
[2]
td2 species the time after DIOR is negated, when the data bus is no longer driven by the device (three-state).
[3]
If IORDY is LOW at tsu4, the host waits until IORDY is made HIGH before the PIO cycle is completed. In that case, tsu5 must be met for
reading (tsu3 does not apply). When IORDY is HIGH at tsu4, tsu3 must be met for reading (tsu5 does not apply).
14.3.2
GDMA slave mode
tsu3(min)
data set-up time before DIOR on
(minimum)
50
35
20
ns
th3(min.)
data hold time after DIOR off (minimum)
55555ns
td2(max)
data to three-state delay after DIOR off
(minimum)
[2] 30
30
ns
th1(min)
address hold time after DIOR/DIOW off
(minimum)
20
15
10
ns
tsu4(min)
IORDY after DIOR/DIOW on set-up time
(minimum)
[3] 35
35
ns
tsu5(min)
read data to IORDY HIGH set-up time
(minimum)
[3] 00000ns
tw3(max)
IORDY LOW pulse width (maximum)
1250
ns
Table 78:
PIO mode timing parameters…continued
VCC = 4.0 to 5.5 V; VGND =0V; Tamb = 40 to +85 °C.
Symbol
Parameter
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Unit
DREQ is continuously asserted until the last transfer is done or the FIFO is full.
Data strobes: DIOR (read), DIOW (write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 19. GDMA slave mode timing (BURST = 00H, MODE = 00H).
th1
tw1
tsu1
td1
tsu2
td2
th2
Tcy1
(write) DATA[15:0]
(read) DATA[15:0]
DREQ (2)
DACK(1)
DIOR/DIOW(1)
MGT500
tsu3
tw2
ta1
th3
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