參數(shù)資料
型號： 935268625551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 22/82頁
文件大小： 1965K
代理商： 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
29 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Remark: The DMA bus defaults to three-state, until a DMA command is executed. All
the other control signals are not three-stated.
9.4.1
DMA Command register (address: 30H)
The DMA Command register is a 1-byte register that initiates all DMA transfer activity
on the DMA Controller. The register is write-only: reading it will return FFH.
Remark: The DMA bus will be in three-state until a DMA command is executed.
DMA Hardware register (see Table 35 and Table 36)
MASTER
set to logic 0
MDMA read/write (opcode = 06H/07H)
DMA Conguration register (see Table 33 and Table 34)
DMA_MODE[1:0]
selects the MDMA mode; timings are ATA(PI) compatible
ATA_MODE
set to logic 1 (ATA transfer)
DMA Hardware register (see Table 35 and Table 36)
MASTER
set to logic 0
UDMA read/write (opcode = 02H/03H)
DMA Conguration register (see Table 33 and Table 34)
DMA_MODE[1:0]
selects the UDMA mode; timings are ATA(PI) compatible
IGNORE_IORDY
used to ignore the IORDY pin during transfer
ATA_MODE
set to logic 1 (ATA transfer)
DMA Hardware register (see Table 35 and Table 36)
MASTER
set to logic 0
Table 27:
Control bits for IDE-specied DMA transfers…continued
Control bits
Description
Table 28:
DMA Command register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DMA_CMD[7:0]
Reset
FFH
Bus reset
FFH
Access
W
Table 29:
DMA Command register: bit description
Bit
Symbol
Description
7:0
DMA_CMD[7:0]
DMA command code, see Table 30.
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