Operating Modes and On-Chip Memory
Memory Map
MC68HC11E Family
—
Rev. 4
Technical Data
MOTOROLA
Operating Modes and On-Chip Memory
77
$1027
Pulse Accumulator Count
Register (PACNT)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indetermnate after reset
$1028
Serial Peripheral Control
Register (SPCR)
See page 173.
Read:
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset:
0
0
0
0
0
1
U
U
$1029
Serial Peripheral Status
Register (SPSR)
See page 175.
Read:
SPIF
WCOL
MODF
Write:
Reset:
0
0
0
0
0
0
0
0
$102A
Serial Peripheral Data I/O
Register (SPDR)
See page 176.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indetermnate after reset
$102B
Baud Rate Register
(BAUD)
See page 157.
Read:
TCLR
SCP2
(1)
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
Write:
Reset:
0
0
0
0
0
U
U
U
$102C
Serial Communications
Control Register 1 (SCCR1)
See page 153.
Read:
R8
T8
M
WAKE
Write:
Reset:
I
I
0
0
0
0
0
0
$102D
Serial Communications
Control Register 2 (SCCR2)
See page 154.
Read:
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Write:
Reset:
0
0
0
0
0
0
0
0
$102E
Serial Communications Status
Register (SCSR)
See page 155.
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
Write:
Reset:
1
1
0
0
0
0
0
0
1. SCP2 adds
÷
39 to SCI prescaler and is present only in MC68HC(7)11E20.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
I = Indetermnate after reset
Figure 4-7. Register and Control Bit Assignments (Sheet 6 of 8)