Operating Modes and On-Chip Memory
Memory Map
MC68HC11E Family
—
Rev. 4
Technical Data
MOTOROLA
Operating Modes and On-Chip Memory
73
$1003
Port C Data Register
(PORTC)
See page 136.
Read:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Write:
Reset:
Indetermnate after reset
$1004
Port B Data Register
(PORTB)
See page 136.
Read:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Write:
Reset:
0
0
0
0
0
0
0
0
$1005
Port C Latched Register
(PORTCL)
See page 137.
Read:
PCL7
PCL6
PCL5
PCL4
PCL3
PCL2
PCL1
PCL0
Write:
Reset:
Indetermnate after reset
$1006
Reserved
R
R
R
R
R
R
R
R
$1007
Port C Data Direction Register
(DDRC)
See page 137.
Read:
DDRC7 DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Write:
Reset:
0
0
0
0
0
0
0
0
$1008
Port D Data Register
(PORTD)
See page 138.
Read:
0
0
PD5
PD4
PD3
PD2
PD1
PD0
Write:
Reset:
U
U
I
I
I
I
I
I
$1009
Port D Data Direction Register
(DDRD)
See page 138.
Read:
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
Write:
Reset:
0
0
0
0
0
0
0
0
$100A
Port E Data Register
(PORTE)
See page 139.
Read:
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Write:
Reset:
Indetermnate after reset
$100B
Timer Compare Force
Register (CFORC)
See page 190.
Read:
FOC1
FOC2
FOC3
FOC4
FOC5
Write:
Reset:
0
0
0
0
0
0
0
0
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
I = Indetermnate after reset
Figure 4-7. Register and Control Bit Assignments (Sheet 2 of 8)