Serial Peripheral Interface (SPI)
SPI Registers
MC68HC11E Family
—
Rev. 4
Technical Data
MOTOROLA
Serial Peripheral Interface (SPI)
175
8.8.2 Serial Peripheral Status Register
SPIF
—
SPI Interrupt Complete Flag
SPIF is set upon completion of data transfer between the processor
and the external device. If SPIF goes high, and if SPIE is set, a serial
peripheral interrupt is generated. To clear the SPIF bit, read the SPSR
with SPIF set, then access the SPDR. Unless SPSR is read (with
SPIF set) first, attempts to write SPDR are inhibited.
WCOL
—
Write Collision Bit
Clearing the WCOL bit is accomplished by reading the SPSR (with
WCOL set) followed by an access of SPDR. Refer to
8.6.4 Slave
Select
and
8.7 SPI System Errors
.
0 = No write collision
1 = Write collision
Bit 5
—
Unimplemented
Always reads 0
MODF
—
Mode Fault Bit
To clear the MODF bit, read the SPSR (with MODF set), then write to
the SPCR. Refer to
8.6.4 Slave Select
and
8.7 SPI System Errors
.
0 = No mode fault
1 = Mode fault
Bits [3:0]
—
Unimplemented
Always read 0
Address:
$1029
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
WCOL
MODF
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-4. Serial Peripheral Status Register (SPSR)