Operating Modes and On-Chip Memory
Memory Map
MC68HC11E Family
—
Rev. 4
Technical Data
MOTOROLA
Operating Modes and On-Chip Memory
69
passes to the loaded program at $0000. Refer to
Figure 4-2
,
Figure 4-3
,
Figure 4-4
,
Figure 4-5
, and
Figure 4-6
.
Use of an external pullup resistor is required when using the SCI
transmitter pin because port D pins are configured for wired-OR
operation by the bootloader. In bootstrap mode, the interrupt vectors are
directed to RAM. This allows the use of interrupts through a jump table.
Refer to the application note AN1060 entitled
M68HC11 Bootstrap
Mode
,
that is included in this data book.
4.4 Memory Map
The operating mode determines memory mapping and whether external
addresses can be accessed. Refer to
Figure 4-2
,
Figure 4-3
,
Figure 4-4
,
Figure 4-5
, and
Figure 4-6
, which illustrate the memory
maps for each of the three families comprising the M68HC11 E series of
MCUs.
Memory locations for on-chip resources are the same for both expanded
and single-chip modes. Control bits in the configuration (CONFIG)
register allow EPROM and EEPROM (if present) to be disabled from the
memory map. The RAM is mapped to $0000 after reset. It can be placed
at any 4-Kbyte boundary ($x000) by writing an appropriate value to the
RAM and I/O map register (INIT). The 64-byte register block is mapped
to $1000 after reset and also can be placed at any 4-Kbyte boundary
($x000) by writing an appropriate value to the INIT register. If RAM and
registers are mapped to the same boundary, the first 64 bytes of RAM
will be inaccessible.
Refer to
Figure 4-7
, which details the MCU register and control bit
assignments. Reset states shown are for single-chip mode only.